The present claimed invention relates to the field of flat panel displays. More specifically, the present claimed invention relates to a flat panel display and methods for forming a flat panel display having a barrier metal for electron emission.
A Cathode Ray Tube (CRT) display generally provides the best brightness, highest contrast, best color quality and largest viewing angle of prior art computer displays. CRT displays typically use a layer of phosphor which is deposited on a thin glass faceplate. These CRTs generate a picture by using one to three electron beams which generate high energy electrons that are scanned across the phosphor in a raster pattern.
The phosphor converts the electron energy into visible light so as to form the desired picture. However, prior art CRT displays are large and bulky due to the large vacuum envelopes that enclose the cathode and extend from the cathode to the faceplate of the display. Therefore, typically, other types of display technologies such as active matrix liquid crystal display, plasma display and electro-luminescent display technologies have been used in the past to form thin displays.
Recently, a thin flat panel display (FPD) has been developed which uses the same process for generating pictures as is used in CRT devices. These flat panel displays use a backplate including a matrix structure of rows and columns of electrodes. One such flat panel display is described in U.S. Pat. No. 5,541,473 which is incorporated herein by reference. Flat panel displays are typically matrixed-addressed and they comprise matrix addressing electrodes. The intersection of each row line and each column line in the matrix defines a pixel, the smallest addressable element in an electronic display.
The essence of electronic displays is the ability to turn on and off individually picture elements (pixels). A typical high information content display will have about a quarter million pixels in a 33 cm diagonal orthogonal array, each under individual control by the electronics. The pixel resolution is normally just at or below the resolving power of the eye. Thus, a good quality picture can be created from a pattern of activated pixels.
One means for generating arrays of field emission cathode structures relies on well established semiconductor micro-fabrication techniques. These techniques produce highly regular arrays of precisely shaped field emission tips. Lithography, generally used in these techniques, involves numerous processing steps, many of them wet. The number of tips per unit area, the size of the tips, and their spacing are determined by the available photoresists and the exposing radiation.
Tips produced by the method are typically cone-shaped with base diameters on the order of 0.5 to 1 xcexcm, heights of anywhere from 0.5 to 2 xcexcm, tip radii of tens of nanometers. This size limits the number of tips per pixel possible for high resolution displays, where large numbers (400-1000 emitters per pixel) are desirable for uniform emission to provide adequate gray levels, and to reduce the current density per tip for stability and long lifetimes. Maintaining two dimensional registry of the periodic tip arrays over large areas, such as large TV-sized screens, can also be a problem for gated field emission constructions by conventional means, resulting in poor yields and high costs.
U.S. Pat. No. 4,338,164 describes a method of preparing planar surfaces having a microstructured protuberances thereon comprising a complicated series of steps involving irradiation of a soluble material (e.g., mica) with high energy ions, as from a heavy ion accelerator, to provide column-like traces in the matrix that are subsequently etched away to be later filled with an appropriate conductive, electron-emitting material. The original soluble material is then dissolved following additional metal deposition steps that provide a conductive substrate for the electron emitting material. The method is said to produce up to 106 emitters per cm2, the emitters having a diameter of approximately 1-2 xcexcm.
U.S. Pat. No. 5,266,530 describes a gated electron field emitter prepared by a complicated series of deposition and etching steps on a substrate, preferably crystalline.
FIG. 1 is a prior art flat CRT cathode of tungsten as a thermionic electron source are placed on a substrate. Scan electrons and data electrodes are formed on a glass plate having a plurality of holes at pixel locations. The electrodes with predetermined voltages applied thereto selectively pass the electrons emitted from the line cathode so that the electrons accelerate toward a screen and excite phosphors coated on the inner surface of the screen. Different types of emitters have been suggested in the past for the flat CRT shown in FIG. 1.
Among these different emitters is the use of carbon nanotubes. In the carbon nanotube displays, a patterned of microstructures are disposed on a row electrode so that when voltage is applied to between the row electrode and a column electrode, electrons are emitted from the cathode to the screen to excite the phosphors on the screen to create images.
FIG. 2 shows a schematic (cross-sectional view) of a portion of a prior art matrixed addressed ungated field emission display device 10 including cathode 20, for one embodiment of the invention. Patterned microstructure layer 12 disposed on row conductors 16 which are supported by substrate 14 provides cathode 20. Transparent column conductors 18 generally indium ion oxide (ITO) are disposed on substrate 22, preferably glass. Which supports a layer of continuous or discontinuous phosphor material 23 and which comprises anode 24 of the invention. Phosphor material 23 is capable of excitation by electrons. Upon applying a voltage from voltage source 26, there results a high electric filed being applied to the emission sites of microstructured layer 12. This causes a flow of electrons across low pressure gas or vacuum gap 28 between column conductors 18 and row conductors 16.
FIG. 3 is another prior art example of a gated matrixed addressed field emission display device 30. The device includes a gated cathode 32 which includes a conductive gate columns 34, insulated spacers 36, patterned microstructured layer 38, deposited on and in electrical contact with row conductors 40 which are supported on substrate 41, generally glass. Cathode 32 is spaced apart from anode 42 by low pressure gas or preferably vacuum gap 44, the space between phosphor 50 and cathode 32. Anode 42 includes substrate 46 on which is located a transparent phosphor containing layer 50.
FIG. 4 shows a cross sectional view of a portion of a prior art carbon nanotube CRT display. The display in FIG. 4 includes a gated cathode, a patterned microstructure layer consisting of carbon nanotube structures, insulated spacers, a patterned microstructure layer deposited on it and electrical contact with row conductors which are supported on the substrate. Cathode is spaced apart from an node structure by a low pressure vacuum. The anode comprises a faceplate, a conductor layer and phosphor which when bombarded with electrons emitted from the cathode excites the phosphor. The nanotube structure shown in FIG. 4 typically includes a resistive layer between the cathode conductors and the microstructure emissive elements. The microstructure emissive elements and the resistive layer are typically constructed in a planar configuration.
FIG. 5 is another example of a carbon nano-tube field emission display device of the prior art. The field emitter of FIG. 5,illustrates a multi-layer structure 300 which is a cross sectional view of a portion of an FED flat panel display. The multi-layer structure 100 comprises a field emission backplate structure 110. An image is generated at faceplate structure 160.
The backplate structure 110 generally comprises of a patterned emitter electrode 120, a resistor layer 115, an electrically insulating layer 140, a gate layer 150 and electron-emissive elements 140 situated in an aperture through insulating layer 135. The electron-emissive elements 140 are carbon based material.
The backplate 110 also includes a catalyst layer upon which the electron-emissive elements 140 are situated. The resistive layer 115 and the catalyst layer 120 gives the structure 100 the uniformity of emitter elements formation that is required to generate the proper imagery in the display. Although the structure 100 shown in FIG. 5 has a vertical structural construction, the catalyst layer and the resistor layer 115 may be fabricated to be planar.
It is typical in the prior art device shown in FIG. 5 to have a nickel (Ni) material as the catalyst layer and a silicon based material (Si) as the resistor layer 115. The catalyst material, in this case Ni, interfaces directly with the resistor 115 material. The interfacing between the catalyst 120 and resistor 115 materials results in a poly-crystalazition process from the inter-diffusion between the catalyst material and the resistor 115 material. The poly-crystallization process often results in lowering the resistive value of the resistor material 115. The poly-crsyatilization of the Ni catalyst and the Si resistor also affects the adhension capabilities of catalyst layer. As the catalyst layer diffuses into the resistor layer 115, the catalyst layer loses the ability to act as an effective adhension layer between the emitter elements 140 and the resistor layer 115. Weakening the adhension capabilities of the catalyst layer makes it difficult to grow the emitter elements 140 and results in a costly fabrication process.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
The present invention furnishes an electron-emitting device having a metal barrier layer patterned to meet the foregoing needs. The present barrier layer contains multiple laterally separated sections situated between electron-emissive elements, on one hand, and emitter electrodes, on the other hand. More specifically, the barrier layer is situated on sections of a catalyst layer. The sections of the catalyst layer are spaced apart along each emitter electrode.
The present invention provides an electron field emission display including an electrode comprising a cathode, a layer comprising a dense array of discrete solid microstructures disposed on at least a portion of one or more surfaces of a substrate, the microstructures having an a real number of density greater than 106/cm2. A portion of the microstructure conformally is over-coated with one or more electron emitting material.
The display further includes an electric field producing structure that comprises first and second conductive electrodes insulately spaced apart and substantially parallel to each other. The first conductive electrode comprises a layer of electron emitting elements, preferably made of nano-structures of carbon, a resistor layer, a catalyst layer to provide emitter distribution unformity and a metal barrier layer that acts as an adhesive layer between the catalyst layer and the resistor layer. The metal layer also acts as an anti-diffusion layer between the resistor and the catalyst layers.
A preferred method of making an electrode for a field emission display device of the present invention comprises the step of providing matirx addressable substrate
To manufacture an electron-emitting device that employs the metal barrier layer of the invention, a structure is typically first provided in which a control electrode overlies a dielectric layer that overlies an electrically conductive catalyst layer overlying an emitter electrode. Electron-emissive elements are situated in a composite opening extending through the control electrode and dielectric layer in the structure so that the electron-emissive element overlies the catalyst layer above the emitter electrode. Creation of the metal barrier sections involves removing portions of the catalyst layer located generally below spaces situated to the sides of the control electrode.
The removing step is normally performed by etching the barrier layer through a mask formed at least partially with the catalyst layer. By utilizing this technique, there is typically no need to perform a separate masking step in order to pattern the catalyst layer into separate sections along the emitter electrode. Also, in the embodiment where portions of the barrier layer are spaced laterally apart below the barrier layer, the barrier layer can be initially patterned using the mask typically employed in patterning an emitter layer to form the emitter electrode. Again, there is no need to perform an extra masking step to provide this initial patterning to the catalyst layer. The net result is that the desired pattern can be provided in the barrier layer without increasing the number of masking steps.